Contents

65c816 ASM Reference v1.0

This is a reference to the 65c816 instructions for the SNES.

How to Read Opcode Descriptions

A key to reading opcodes descriptions used in this file.

65c816 Opcode List

The list of instructions and their descriptions.


Reading opcode descriptions
How to Read Opcode Descriptions

This section describes the format for each description of opcodes.

The general layout for each opcode description is as follows:

ADC dp	nv----zc	65 xx

The first part is the instruction itself.  This description is for a ADC instruction.  The second part ( the dp ) is the addressing mode.  Other addressing modes are described below.  The third part are flags that are affected by this instruction.  For the ADC instruction, the negative, overflow, zero and carry flags are affected.  The last part is the opcode.  The ADC dp instruction will output a 65 hex followed by the direct page value.

The following is a list of addressing modes used in the description:

imm8/16	Immediate (8/16-bit value)

dp	Direct

abs	Absolute

long	Absolute Long

A	Accumulator

(dp), y	Direct Indirect Indexed with Y

[dp], y	Direct Indirect Indexed Long with Y

(dp, x)	Direct Indexed with X Indirect

dp, x	Direct Indexed with X

dp, y	Direct Indexed with Y

abs, x	Absolute Indexed with X

long, x	Absolute Long Indexed with X

abs, y	Absolute Indexed with Y

pcr	Program Counter Relative

pcrlong	Program Counter Relative Long

(abs)	Absolute Indirect

(abs, x)	Absolute Indexed with X Indirect

(dp)	Direct Indirect

[dp]	Direct Indirect Long

sr, s	Stack Relative

(sr, s), y	Stack Relative Indirect Indexed with Y

srcbank, destbank	Block Move


65c816 Opcode List

This is the list of 65c816 opcode instructions.

ADC	Add with carry

AND	AND Accumulator with Memory

ASL	Left Shift Accumulator or Memory

BCC	Branch if Carry Clear

BCS	Branch if Carry Set

BEQ	Branch if Equal

BIT	Bit Test

BMI	Branch if Minus

BNE	Branch if not Equal

BPL	Branch if Plus

BRA	Branch Always

BRK	Software Break

BRL	Branch Always Long

BVC	Branch if Overflow Clear

BVS	Branch if Overflow Set

CLC	Clear Carry Flag

CLD	Clear Decimal Flag

CLI	Clear Interrupt Flag

CLV	Clear Overflow Flag

CMP	Compare Accumulator with Memory

COP	Coprocessor Empowerment

CPX	Compare X with Memory

CPY	Compare Y with Memory

DEC	Decrement Accumulator or Memory

DEX	Decrement X

DEY	Decrement Y

EOR	Exclusive OR Accumulator with Memory

INC	Increment Accumulator or Memory

INX	Increment X

INY	Increment Y

JML	Jump Long

JMP	Jump

JSL	Jump to Subroutine Long

JSR	Jump to Subroutine

LDA	Load Accumulator from Memory

LDX	Load X from Memory

LDY	Load Y from Memory

LSR	Shift Right Accumulator or Memory

MVN	Block Move Negative

MVP	Block Move Positive

NOP	No operation

ORA	OR Accumulator with Memory

PEA	Push Effective Address

PEI	Push Effective Indirect Address

PER	Push Program Counter Relative

PHA	Push Accumulator

PHB	Push Data Bank Register

PHD	Push Direct Page Register

PHK	Push Program Bank Register

PHP	Push Processor Status Flags

PHX	Push X

PHY	Push Y

PLA	Pull Accumulator

PLB	Pull Data Bank Register

PLD	Pull Direct Page Register

PLP	Pull Processor Status Flags

PLX	Pull X

PLY	Pull Y

REP	Reset Processor Status

ROL	Rotate Left Accumulator or Memory

ROR	Rotate Right Accumulator or Memory

RTI	Return from Interrupt

RTL	Return from Subroutine Long

RTS	Return from Subroutine

SBC	Subtract with Carry

SEC	Set Carry Flag

SED	Set Decimal Flag

SEI	Set Interrupt Flag

SEP	Set Processor Status Flag

STA	Store Accumulator to Memory

STP	Stop the Clock

STX	Store X to Memory

STY	Store Y to Memory

STZ	Store Zero to Memory

TAX	Transfer Accumulator to X

TAY	Transfer Accumulator to Y

TCD	Transfer Accumulator to Direct Page

TCS	Transfer Accumulator to Stack

TDC	Transfer Direct Page to Accumulator

TRB	Test and Reset Bit

TSB	Test and Set Bit

TSC	Transfer Stack to Accumulator

TSX	Transfer Stack to X

TXA	Transfer X to Accumulator

TXS	Transfer X to Stack

TXY	Transfer X to Y

TYA	Transfer Y to Accumulator

TYX	Transfer Y to X

WAI	Wait for Interrupt

XBA	Exchanges B and A

XCE	Exchange Carry and Emulation


ADC: Add with Carry

ADC imm8/16	nv----zc	69 xx xx

ADC dp	nv----zc	65 xx

ADC abs	nv----zc	6D xx xx

ADC long	nv----zc	6F xx xx xx

ADC dp, x	nv----zc	75 xx

ADC abs, x	nv----zc	7D xx xx

ADC abs, y	nv----zc	79 xx xx

ADC long, x	nv----zc	7F xx xx xx

ADC (dp)	nv----zc	72 xx

ADC (dp), y	nv----zc	71 xx

ADC [dp]	nv----zc	67 xx

ADC [dp], y	nv----zc	77 xx

ADC (dp, x)	nv----zc	61 xx

ADC sr, s	nv----zc	63 xx

ADC (sr, s), y	nv----zc	73 xx

ADC adds the operand to the accumulator. If the carry flag is set, 1 is also added.

eg.

A: 0010	CLC	; clear carry flag

A: 0010	ADC #$50	; adds $50 to accumulator

A: 0060	; result


AND: AND Accumulator with Memory

AND imm8/16	n-----z-	29 xx xx

AND dp	n-----z-	35 xx

AND abs	n-----z-	2D xx xx

AND long	n-----z-	2F xx xx xx

AND dp, x	n-----z-	35 xx

AND abs, x	n-----z-	3D xx xx

AND abs, y	n-----z-	39 xx xx

AND long, x	n-----z-	3F xx xx xx

AND (dp)	n-----z-	32 xx

AND (dp), y	n-----z-	31 xx

AND [dp]	n-----z-	27 xx

AND [dp], y	n-----z-	37 xx

AND (dp, x)	n-----z-	21 xx

AND sr, s	n-----z-	23 xx

AND (sr, s), y	n-----z-	33 xx

AND performs bitwise AND to the Accumulator and the operand and stores the result back into the Accumulator.

eg.

A: 0010	AND #$80	; AND $80 with Accumulator

A: 0000	; Result is 0


Logical Shift Instructions
ASL, LSR: Logical Shift Instructions

ASL A	n-----zc	0A

ASL dp	n-----zc	06 xx

ASL dp, x	n-----zc	16 xx

ASL abs	n-----zc	0E xx xx

ASL abs, x	n-----zc	1E xx xx

LSR A	n-----zc	4A

LSR dp	n-----zc	46 xx

LSR dp, x	n-----zc	56 xx

LSR abs	n-----zc	4E xx xx

LSR abs, x	n-----zc	5E xx xx

ASL instruction left shifts the operand by 1 bit. LSR instruction right shifts the operand by 1.

eg.

A: 0010	ASL	; Left shift Accumulator

A: 0020


Branch Instructions
BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BRL, BVC, BVS: Branch Instructions

BCC pcr or BLT pcr	--------	90 xx

BCS pcr or BGT pcr	--------	B0 xx

BEQ pcr	--------	F0 xx

BNE pcr	--------	DO xx

BMI pcr	--------	30 xx

BPL pcr	--------	10 xx

BRA pcr	--------	80 xx

BRL pcrlong	--------	82 xx xx

BVC pcr	--------	50 xx

BVS pcr	--------	70 xx

The branch instructions branches to a another part of the code if the conditions are met. Here is a table of which conditions are required for each branch instruction.

Instruction	Will branch if. . .

BCC	Carry flag is clear

BCS	Carry flag is set

BEQ	Zero flag set

BNE	Zero flag clear

BMI	Negative flag set

BPL	Negative flag clear

BVC	Overflow flag clear

BVS	Overflow flag set

The BRA and BRL are unconditional branch instructions. They will branch always (like a JMP instruction). The BGE (Branch if greater than) and BLT (Branch if less than) are aliases for the BCS and BCC respectively.

Branch instructions have a 128 byte range; however, the BRL instruction has a 32768 byte range. Usually, instead of specifying the ± PC relative range for the branch instructions, most disassemblers often show branch instructions as taking an abs addressing mode.

eg.

X: 0050 P: ---x-i--	CPX #$0050	; compare X with 50

X: 0050 P: ---x-iz-	BEQ next	; will branch to next

.

.

.

next:


BIT: Bit Test

BIT imm8/16	------z-	89 xx xx

BIT dp	nv----z-	24 xx

BIT dp, x	nv----z-	34 xx

BIT abs	nv----z-	2C xx xx

BIT abs, x	nv----z-	3C xx xx

BIT performs AND with the Accumulator and the operand; however, the flags are affected but the result is not stored.

eg.

A: 0010 P: ---x-i--	BIT #$0080 ; Bits are tested

A: 0010 P: ---x-iz-            ; Result not stored


BRK: Software Break

BRK imm8	----di--	00 xx

BRK causes a software break. The imm8 operand is not required to be specified.


Flag Clear Instructions
CLC, CLD, CLI, CLV: Flag Clear Instructions

CLC	-------c	18

CLD	----d---	D8

CLI	-----i--	58

CLV	-v------	B8

These instructions clears certain flags. CLC clears the carry flag; CLD clears the decimal flag; CLI clears the interrupt flag; CLV clears the overflow flag.


Compare Instructions
CMP, CPX, CPY: Compare Instructions

CMP imm8/16	n-----zc	C9 xx xx

CMP dp	n-----zc	C5 xx

CMP abs	n-----zc	CD xx xx

CMP long	n-----zc	CF xx xx xx

CMP dp, x	n-----zc	D5 xx

CMP abs, x	n-----zc	DD xx xx

CMP abs, y	n-----zc	D9 xx xx

CMP long, x	n-----zc	DF xx xx xx

CMP (dp)	n-----zc	D2 xx

CMP (dp), y	n-----zc	D1 xx

CMP [dp]	n-----zc	C7 xx

CMP [dp], y	n-----zc	D7 xx

CMP (dp, x)	n-----zc	C1 xx

CMP sr, s	n-----zc	C3 xx

CMP (sr, s), y	n-----zc	D3 xx

CPX imm8/16	n-----zc	E0 xx xx

CPX dp	n-----zc	E4 xx

CPX abs	n-----zc	EC xx xx

CPY imm8/16	n-----zc	C0 xx xx

CPY dp	n-----zc	C4 xx

CPY abs	n-----zc	EC xx xx

These instructions compares a register with memory. The CMP instruction compares the Accumulator with memory; the CPX instruction compares X with memory; the CPY instruction compares Y with memory. The flags are set as if the operand was 'subtracted' from the register. The zero flag is set if both the register and the operand are equal. The carry flag is set if the operand is greater than the register. The negative flag is set if the result was negative.

A: 0020 P: --mx-i--	cmp #$20	; compare accumulator with $20

; if equal, z flag is set

A: 0020 P: --mx-iz-	beq next	; branch if equal (ZF=1)


COP: Coprocessor Empowerment

COP imm8	----di--	02 xx

COP generates a software interrupt.


Decrement Instructions
DEC, DEX, DEY: Decrement Instructions

DEC A	n-----z-	3A

DEC dp	n-----z-	C6 xx

DEC dp, x	n-----z-	D6 xx

DEC abs	n-----z-	CE

DEC abs, x	n-----z-	DE

DEX	n-----z-	CA

DEY	n-----z-	88

The decrement instructions decrement the operand by 1. The DEX instruction decrements X by 1; the DEY instruction decrements Y by 1.

eg.

A: 0001	DEC	; Decrement Accumulator by 1

A: 0000


EOR: Exclusive OR Accumulator with Memory

EOR imm8/16	n-----z-	49 xx xx

EOR dp	n-----z-	45 xx

EOR abs	n-----z-	4D xx xx

EOR long	n-----z-	4F xx xx xx

EOR dp, x	n-----z-	55 xx

EOR abs, x	n-----z-	5D xx xx

EOR abs, y	n-----z-	59 xx xx

EOR long, x	n-----z-	5F xx xx xx

EOR (dp)	n-----z-	52 xx

EOR (dp), y	n-----z-	51 xx

EOR [dp]	n-----z-	47 xx

EOR [dp], y	n-----z-	57 xx

EOR (dp, x)	n-----z-	41 xx

EOR sr, s	n-----z-	43 xx

EOR (sr, s), y	n-----z-	53 xx

EOR performs bitwise exclusive OR between the Accumulator and the operand. The result is stored in the Accumulator.

eg.

A: FFFF	EOR #$DDDD ; Exclusive OR

A: 2222


Increment Instructions
INC, INX, INY: Increment Instructions

INC A	n-----z-	1A

INC dp	n-----z-	E6 xx

INC dp, x	n-----z-	F6 xx

INC abs	n-----z-	EE xx xx

INC abs, x	n-----z-	FE xx xx

INX	n-----z-	E8

INY	n-----z-	C8

The increment instructions increment the operand by 1. The INX instruction increments X by 1; the INY instruction increments Y by 1.

eg.

A: 0000	INC	; Increment Accumulator

A: 0001


JMP: Jump

JMP abs	--------	4C xx xx

JMP long or JML long	--------	5C xx xx xx

JMP (abs)	--------	6C xx xx

JMP (abs, x)	--------	7C xx xx

JMP [abs] or JML [abs]	--------	DC xx xx

JMP instruction jumps to another address. JML is an alias form of the JMP long, which is used to jump to locations outside the current bank.

eg.

PBR: 80	JMP $5500	; Jumps to $80:5500

PBR: 80	JML $908000	; Long jumps to $90:8000

PBR: 90


JSR: Jump to Subroutine

JSR abs	--------	20 xx xx

JSR long or JSL long	--------	22 xx xx xx

JSR (abs, x)	--------	FC xx xx

JSR jump to a new location while saving the current program counter. This is done by pushing the program counter onto the stack, then jumping to the location. The JSL instruction is an alias for JSR long.

In order for the user to return from the subroutine back to the originally saved program counter, a RTS or RTL instruction must be executed.

eg.

PC: 8090	JSR $9000	; Jump to subroutine at $9000

PC: 9000	.

.

.

RTS	; Return from subroutine

PC: 8093


Register Load Instructions
LDA, LDX, LDY: Register Load Instructions

LDA imm8/16	n-----z-	A9 xx xx

LDA dp	n-----z-	A5 xx

LDA abs	n-----z-	AD xx xx

LDA long	n-----z-	AF xx xx xx

LDA dp, x	n-----z-	B5 xx

LDA abs, x	n-----z-	BD xx xx

LDA abs, y	n-----z-	B9 xx xx

LDA long, x	n-----z-	BF xx xx xx

LDA (dp)	n-----z-	B2 xx

LDA (dp), y	n-----z-	B1 xx

LDA [dp]	n-----z-	A7 xx

LDA [dp], y	n-----z-	B7 xx

LDA (dp, x)	n-----z-	A1 xx

LDA  sr, s	n-----z-	A3 xx

LDA (sr, s), y	n-----z-	B3 xx

LDX imm8/16	n-----z-	A2 xx xx

LDX dp	n-----z-	A6 xx

LDX dp, y	n-----z-	B6 xx

LDX abs	n-----z-	AE xx xx

LDX abs, y	n-----z-	BE xx xx

LDY imm8/16	n-----z-	A0 xx xx

LDY dp	n-----z-	A4 xx

LDY dp, y	n-----z-	B4 xx

LDY abs	n-----z-	AC xx xx

LDY abs, y	n-----z-	BC xx xx

These instructions loads a value from the operand to a register. LDA instruction loads to the accumulator; LDX instruction loads to X, LDY instructions loads to Y.

eg.

A: 2390	LDA #$FFFF

A: FFFF


Block Move Instructions
MVP, MVN: Block Move Instructions

MVP srcbank, destbank	--------	44 xx xx

MVN srcbank, destbank	--------	54 xx xx

These instructions move data from one place to another. The X register must be loaded with the lower 16-bits of the source address; the Y register must be loaded with the lower 16-bits of the destination address. The Accumulator should be loaded with the number of bytes to copy. The banks of the source and destination address are specified in the first 2 operands of the MVN or MVP instruction. The difference between MVP and MVN instructions is the direction in which the data is transferred.

eg.

; Transfers 5 bytes from $80:8000 -> $90:8000

A: 0005 X: 8000 Y: 8000	MVP $80, $90


NOP: No Operation

NOP	--------	EA

Does nothing.


ORA: OR Accumulator or Memory

ORA imm8/16	n-----z-	09 xx xx

ORA dp	n-----z-	05 xx

ORA abs	n-----z-	0D xx xx

ORA long	n-----z-	0F xx xx xx

ORA dp, x	n-----z-	15 xx

ORA abs, x	n-----z-	1D xx xx

ORA abs, y	n-----z-	19 xx xx

ORA long, x	n-----z-	1F xx xx xx

ORA (dp)	n-----z-	12 xx

ORA (dp), y	n-----z-	11 xx

ORA [dp]	n-----z-	07 xx

ORA [dp], y	n-----z-	17 xx

ORA (dp, x)	n-----z-	01 xx

ORA sr, s	n-----z-	03 xx

ORA (sr, s), y	n-----z-	13 xx

ORA performs bitwise OR to the Accumulator or the operand.

eg.

A: 005F	ORA #$7F

A: 007F


PEA: Push Effective Address

PEA abs	--------	F4 xx xx

PEA pushes a 16-bit address onto the stack. The stack pointer is decremented by 2. This instruction is quite misleading since it is the address that is pushed on the stack, not the value stored at that address.

eg.

PEA $6000	; Pushes the value $6000 onto the stack


PEI: Push Effective Indirect Address

PEI (dp)	--------	D4 xx

PEI pushes a 16-bit value from the indirect dp address.

eg.

PEI ($00)	; Pushes the 16-bit value at $00 onto the stack


PER: Push Program Counter Relative

PER pcrlong	--------	62 xx xx

PER pushes a 16-bit value indirectly from the address relative to the current PC.

eg.

PC: 8000	PER data	; pushes $FFFF

.

.

.

PC: 8900	data: dcw $FFFF


Register Push Instructions
PHA, PHB, PHD, PHK, PHP, PHX, PHY: Register Push Instructions

PHA	--------	48

PHB	--------	8B

PHD	--------	0B

PHK	--------	4B

PHP	--------	08

PHX	--------	DA

PHY	--------	5A

The register push instructions pushes the value of the register onto the stack. Below is a table of what each instruction does:

PHA	Pushes Accumulator

PHB	Pushes the Data Bank Register

PHD	Pushes the Direct Page Register

PHK	Pushes the Program Bank Register

PHP	Pushes the Processor Status Register

PHX	Pushes the X Register

PHY	Pushes the Y Register


Register Pull Instructions
PLA, PLB, PLD, PLP, PLX, PLY: Register Pull Instructions

PLA	--------	68

PLB	--------	AB

PLD	--------	2B

PLP	--------	28

PLX	--------	FA

PLY	--------	7A

The register pull instructions pulls a value off the stack and into the register. The description of each registers are as follows:

PLA	Pull Accumlator

PLB	Pull Data Bank Register

PLD	Pull Direct Page Register

PLP	Pull Processor Status Register

PLX	Pull X Register

PLY	Pull Y Register


REP: Reset Processor Status

REP imm8	nvmxdizc	C2 xx

REP clears the bits in the processor status specified in the operand.

eg.

P: --mx-i--	REP #$30	; Clear m and x flags

P: -----i--


Bitwise Rotate Instructions
ROL, ROR: Bitwise Rotate Instructions

ROL A	n-----zc	2A

ROL dp	n-----zc	26 xx

ROL dp, X	n-----zc	36 xx

ROL abs	n-----zc	2E xx xx

ROL abs, x	n-----zc	3E xx xx

ROR A	n-----zc	6A

ROR dp	n-----zc	66 xx

ROR dp, x	n-----zc	76 xx

ROR abs	n-----zc	6E xx xx

ROR abs, x	n-----zc	7E xx xx

ROL and ROR performs bitwise rotate to the Accumulator or the operand. ROL rotates left by 1 bit; ROR rotates right by 1 bit. The rotation performed is a 9/15-bit rotate involving the carry flag. In ROL, the left most bit of the operand is shifted into the carry flag and the previous value of the carry flag is shifted into the lo-bit of the operand.  ROR, is the reverse.

eg.

A: 8000	SEC

A: 8000	ROL ; Rotate left 1 bit

A: 0001


Return from Subroutine
RTI, RTS, RTL: Return from Subroutine

RTI	nvmxdizc	40

RTL	--------	6B

RTS	--------	60

These instructions return from a subroutine by pulling the address previously saved by a JSR instruction into the PBR:PC. The RTS is a short return: it is used with a short jump to subroutine and returns by pulling PC. RTL is a long return: it returns from a long jump to subroutine and return by pulling to both PBR and PC. RTI is a return from interrupt, and is only used to return from an interrupt handler.


SBC: Subtract with Carry

SBC imm8/16	nv----zc	E9 xx xx

SBC dp	nv----zc	E5 xx

SBC abs	nv----zc	ED xx xx

SBC long	nv----zc	EF xx xx xx

SBC dp, x	nv----zc	F5 xx

SBC abs, x	nv----zc	FD xx xx

SBC abs, y	nv----zc	F9 xx xx

SBC long, x	nv----zc	FF xx xx xx

SBC (dp)	nv----zc	F2 xx

SBC (dp), y	nv----zc	F1 xx

SBC [dp]	nv----zc	E7 xx

SBC [dp], y	nv----zc	F7 xx

SBC (dp, x)	nv----zc	E1 xx

SBC sr, s	nv----zc	E3 xx

SBC (sr, s), y	nv----zc	F3 xx

SBC subtracts the operand from the Accumulator. An additional 1 is subtracted if carry is set.

eg.

A: 0060	CLC	; clear carry flag

A: 0060	SBC #$50	; subtract $50 to accumulator

A: 0010	; result


Flag Set Instructions
SEC, SED, SEI: Flag Set Instructions

SEC	-------c	38

SED	----d---	F8

SEI	-----i--	78

These instructions sets specific flags. SEC sets the carry flag; SED sets the decimal flag; SEI sets the interrupt flag.


SEP: Set Processor Status

SEP imm8	nvmxdizc	E2 xx

SEP sets the processor status flags with the bits in the operand.

eg.

P: -----i--	SEP #$30	; Set m and x flags

P: --mx-i--


Register Store Instructions
STA, STX, STY: Register Store Instructions

STA imm8/16	n-----z-	89 xx xx

STA dp	n-----z-	85 xx

STA abs	n-----z-	8D xx xx

STA long	n-----z-	8F xx xx xx

STA dp, x	n-----z-	95 xx

STA abs, x	n-----z-	9D xx xx

STA abs, y	n-----z-	99 xx xx

STA long, x	n-----z-	9F xx xx xx

STA (dp)	n-----z-	92 xx

STA (dp), y	n-----z-	91 xx

STA [dp]	n-----z-	87 xx

STA [dp], y	n-----z-	97 xx

STA (dp, x)	n-----z-	81 xx

STA sr, s	n-----z-	83 xx

STA (sr, s), y	n-----z-	93 xx

STX dp	n-----z-	86 xx

STX dp, y	n-----z-	96 xx

STX abs	n-----z-	8E xx xx

STY dp	n-----z-	84 xx

STY dp, y	n-----z-	94 xx

STY abs	n-----z-	8C xx xx

These instructions stores the value in the register to the operand. STA stores the Accumulator to memory; STX stores X to memory; STY stores Y to memory.

eg.

A: 000F	SEP #$20

A: 000F	STA $2100	; store $0F to address $2100


STP: Stop the Clock

STP	--------	DB

Stops the clock.


STZ: Store Zero to Memory

STZ dp	--------	64 xx

STZ dp, x	--------	74 xx

STZ abs	--------	9C xx xx

STZ abs, x	--------	9E xx xx

STZ stores zero to the operand.

eg.

STZ $2100	; store 0 to address $2100


Transfer Instructions
TAX, TAY, TCD, TCS, TDC, TSC, TSX, TXA, TXS, TXY, TYA, TYX: Transfer Instructions

TAX	n------z	AA

TAY	n------z	A8

TCD	n------z	5B

TCS	--------	1B

TDC	n------z	7B

TSC	n------z	3B

TSX	n------z	BA

TXA	n------z	8A

TXS	--------	9A

TXY	n------z	9B

TYA	n------z	98

TYX	n------z	BB

These instructions transfers values from one register to another. The description for each one follows:

TAX	Transfer Accumulator to X

TAY	Transfer Accumulator to Y

TCD	Transfer Accumulator to Direct Page Register

TCS	Transfer Accumulator to Stack Register

TDC	Transfer Direct Page Register to Accumulator

TSC	Transfer Stack Register to Accumulator

TSX	Transfer Stack Register to X

TXA	Transfer X to Accumulator

TXS	Transfer X to Stack Register

TXY	Transfer X to Y

TYA	Transfer Y to A

TYX	Transfer Y to X


Test Bit and Modify Instructions
TRB, TSB: Test Bit and Modify Instructions

TRB dp	------z-	14 xx

TRB abs	------z-	1C xx xx

TSB dp	------z-	04 xx

TSB abs	------z-	0C xx xx

These instructions tests the bits similarly to the BIT instruction, however, the bits are either also set if the TSB instruction is used, or the bits are cleared if the TRB instruction is used.


WAI: Wait for Interrupt

WAI	--------	CB

Waits for the next interrupt before proceeding.


XBA: Exchange B and A

XBA	n------z	EB

Swaps the upper 16 bit of the accumulator with the lower 16-bits.

eg.

A: 5690	XBA

A: 9056


XCE: Exchange Carry and Emulation

XCE	--mx---c	FB

Exchanges the carry flag with the emulation bit to change between Native and Emulation mode.